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INTEGRATED CIRCUITS
PLC18V8Z Zero standby power CMOS versatile PAL devices
Product specification Replaces data sheet PLC18V8Z35/PLC18V8ZI of Dec 19 1995, and data sheet PLC18V8Z25/PLC18V8ZI of Dec 19, 1995 1997 Aug 08
Philips Semiconductors
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
* Industrial control * Medical Instruments * Portable communications equipment
PIN CONFIGURATIONS
PLC18V8Z
DESCRIPTION
The PLC18V8Z is a universal PAL(R) device featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTL/CMOS logic. While compatible with TTL and HCT logic, the PLC18V8Z can also replace HC logic over the VCC range of 4.5 to 5.5V. The PLC18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. Each output features an "Output Macro Cell" which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100A and active power consumption of 1.5mA/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers. The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40C to +85C and supply voltage of 4.5V to 5.5V. Ordering information can be found on the following page.
D, DB, DH, N, Packages
I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 20 VCC 19 F7 18 F6 17 F5 16 F4 15 F3 14 F2 13 F1 12 F0 11 I9/OE
GND 10
D = Plasitc Small Outline Large Package (300mil-wide) DB = Plastic Shrink Small Outline Package (5.3mm wide) DH = Plastic Thin Shrink Small Outline Package (4.4mm wide) N = Plastic Dual In-Line Package (DIP) (300mil-wide)
A Package
I2 I0/ I1 CLK VCC F7 2 1 20 19 18 F6 17 F5 16 F4 15 F3 14 F2 9 10 11 12 13
FEATURES
3 I3 I4 I5 I6 I7 4 5 6 7 8
* 20-pin Universal Programmable Array Logic * Virtually Zero-Standby-power
- 20A (typical)
* Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink Small
Outline), and TSSOP (Thin Shrink Small Outline) packages
* Functional replacement for Series 20 PAL devices * Up to 18 inputs and 8 input/output macro cells * Programmable output polarity * Power-up reset on all registers * Register Preload capability * Synchronous Preset/Asynchronous Reset * Security fuse to prevent duplication of proprietary designs * Also available in 3V operation-the P3C18V8Z
APPLICATIONS
- IOL = 24mA
I8 GND I9/ F0 F1 OE A = Plastic Leaded Chip Carrier
SP00544
PIN DESCRIPTIONS
I B O D F CLK OE Dedicated Input Bidirectional input/output Dedicated output Registered output (D-type flip-flop) Output/Input Macrocell Clock Input Output Enable Supply Voltage Ground
* Battery powered instruments * Laptop and pocket computers
VCC GND
PAL is a registered trademark of Advanced Micro Devices, Inc.
1997 Aug 08
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853-2016 18258
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
ORDERING INFORMATION
DESCRIPTION 20-Pin (300mil-wide) Plastic Dual In-Line Package, 25ns tPD 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package 20-Pin (300mil-wide) Plastic Dual In-Line Package. 35ns tPD 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil square) Plastic Small Outline Large Package Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin shrink Small Outline Package 20-Pin (300mil-wide) Plastic Dual In-Line Package 25ns tPD 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package 20-Pin (300mil-wide) Plastic Dual In-Line Package, 40ns tPD 20-Pin (350mil square) Plastic Leaded chip Carrier Package 20-Pin (300mil square) Plastic Small Outline Large Package 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package Industrial Temperature Range 10% Power Supplies Commercial Temperature Range 5% Power Supplies TEMPERATURE RANGE ORDER CODE PLC18V8Z25N PLC18V8Z25A PLC18V8Z25D PLC18V8Z25DB PLC18V8Z25DH PLC18V8Z35N PLC18V8Z35A PLC18V8Z35D PLC18V8Z35DB PLC18V8Z35DH PLC18V8ZIAN PLC18V8ZIAA PLC18V8ZIAD PLC18V8ZIADB PLC18V8ZIADH PLC18V8ZIN PLC18V8ZIA PLC18V8ZZID PLC18V8ZIDB PLC18V8ZIDH DRAWING NUMBER SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT360-1 SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT260-1 SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT360-1 SOT146-1 SOT380-1 SOT163-1 SOT339-1 SOT360-1
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE
PIN NO. 1 19 18 17 16 15 14 13 12 11 PLC 18V8Z I0/CLK F7 F6 F5 F4 F3 F2 F1 F0 I9/OE 16L8 16H8 16P8 16P8 I B B B B B B B B I 16R4 16RP4 CLK B B D D D D B B OE 16R6 16RP6 CLK B D D D D D D B OE 16R8 16RP8 CLK D D D D D D D D OE 16L2 16H2 16P2 I I I I O O I I I I 14L4 14H4 14P4 I I I O O O O I I I 12L6 12H6 12P6 I I O O O O O O I I 10L8 10H8 10P8 I O O O O O O O O I
The Philips Semiconductors' state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed.
FUNCTIONAL DIAGRAM
I0/ CLK 9 I1 PROGRAMMABLE AND ARRAY 36 ROWS X 72 COLUMNS OMC CLK 9 OMC F6 F7 I0 CONFIG. CELL
I2
9 OMC F1
I7
9 I8 SP AR OE OMC F0 CONFIG. CELL I9
I9/OE
SP00013
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
LOGIC DIAGRAM
0 I0/CLK 1 DIR SP 4 8 12 16 20 24 28 32 35 CLK
I1 2 DIR
AC1 AC2 AR CLK SP OE
19 F7
I2
3 DIR
AC1 AC2 AR CLK SP OE
18 F6
I3
4 DIR
AC1 AC2 AR CLK OE SP
17 F5
I4
5 DIR
AC1 AC2 AR CLK OE SP
16 F4
I5
6 DIR
AC1 AC2 AR CLK OE SP
15 F3
I6
7 DIR
AC1 AC2 AR CLK OE SP
14 F2
I7
8 DIR
AC1 AC2 AR CLK OE SP
13 F1
I8
9 SP AR
AC1 AC2 AR CLK OE
12 F0
11 I9/OE CONFIG. CELL I1 I1 F7 F7 I2 I2 F6 F6 I3 I3 F5 F5 I4 I4 F4 F4 I5 I5 F3 F3 I6 I6 F2 F2 I7 I7 F1 F1 I8 I8 F0 F0 I0 I0 I9 I9 NOTES: In the unprogrammed or virgin state: All cells are in a conductive state. All AND gate locations are pulled to a logic "0" (Low). Output polarity is inverting.
Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direction term. Denotes a programmable cell location. SP00012
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
OUTPUT MACRO CELL (OMC)
1
FROM AND ARRAY
TO ALL OMCs
DIRECTION CONTROL TERM
11 VCC 01 OE 00 MUX SP AR 10
FROM AND ARRAY
{
AC1n AC2n
S D X(n) OUTPUT POLARITY CONTROL Q CLK
01 10 OUT 11 MUX 00
F
00 F 10 MUX 11 01
TO ALL OMCs 11 NOTE: Denotes a programmable cell location. OE
SP00014
THE OUTPUT MACRO CELL (OMC)
The PLC18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional I/O pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions. Each OMC can be independently programmed via 16 architecture control bits, AC1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration.
DESIGN SECURITY
The PLC18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.
1997 Aug 08
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
CONFIGURATION CELL
A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable for all registered OMCs is common--from Pin 11 only. Output enable control of the bidirectional I/O OMCs is provided from the AND array via the direction product term.
If any one OMC is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows: Pin 1 = CLK, Pin 11 = OE Pin 1 and Pin 11 = Input L H
CONTROL CELL CONFIGURATIONS FUNCTION Registered mode Bidirectional I/O mode1 Fixed input mode Fixed output mode AC11 Programmed Unprogrammed Unprogrammed Programmed AC2N Programmed Unprogrammed Programmed Unprogrammed CONFIG. CELL Programmed Unprogrammed Unprogrammed Unprogrammed COMMENTS Dedicated clock from Pin 1. OE Control for all registerd OMCs from Pin 11 only. Pins 1 and 11 are dedicated inputs. 3-State control from AND array only. Pins 1 and 11 are dedicated inputs. Pins 1 and 11 are dedicated inputs. The feedback path (via FMUX) is disabled.
NOTE: 1. This is the virgin state as shipped from the factory.
ARCHITECTURE CONTROL--AC1 and AC2
11 OE DIR SP AR S Q F(D), F (D) S F(B), F (B) CLK S F(O), F (O)
1
OMC CONFIGURATION REGISTERED (D-TYPE)
CODE D
OMC CONFIGURATION BIDIRECTIONAL I/O1 (COMBINATORIAL)
CODE B
OMC CONFIGURATION FIXED OUTPUT
CODE O
1 CLK Q
1 NC SP AR OE NC OE 11 11 CLK Q
SP F (I) AR
F(D), F (D)
OMC CONFIGURATION FIXED INPUT
CODE I
CONFIGURATION CELL PIN 1 = CLK PIN 11 = OE
CODE L
CONFIGURATION CELL PIN 1 = INPUT PIN 11 = INPUT
CODE H6
SP00015
NOTES: A factory shipped unprogrammed device is configured such that: 1. This is the initial unprogrammed state. All cells are in a conductive state. 2. All AND gates are pulled to a logic "0" (Low). 3. Output polarity is inverting. 4. Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled. 5. All Output Macro Cells (OMCs) are configured as bidirectional I/O, with the outputs disabled via the direction term. 6. This configuration cannot be used if any OMCs are configured as registered (Code = D).
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC VCC VIN VOUT t/V IIN IOUT Tamb Tstg Supply voltage Operating supply voltage Input voltage Output voltage Input/clock transition rise or Input currents Output currents Operating temperature range Storage temperature range fall2 PARAMETER RATINGS -0.5 to +7 4.5 to 5.5 (Industrial) 4.75 to 5.25 (Commercial) -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 250 -10 to +10 +24 -40 to +85 (Industrial) 0 to +75 (Commercial) -65 to +150 UNIT VDC VDC VDC VDC ns/V maximum mA mA C C
NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. All digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. For this reason, Schmitt-triggers are recommended if rise/fall times are likely to exceed 250ns at VCC = 4.5V.
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
VOLTAGE WAVEFORMS
+3.0V 90%
10% 0V 5ns tR tF 5ns
AC TEST CONDITIONS
VCC +5V S1
+3.0V 90%
10% 0V 5ns 5ns
C1
C2 I0 BY
R1
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
INPUTS I9 BW BX DUT R2 CL
SP00017
GND
BZ
OUTPUTS
NOTE: C1 and C2 are to bypass VCC to GND.
SP00006
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
Commercial = 0C Tamb +75C, 4.75V VCC 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V LIMITS SYMBOL Input voltage VIL VIH Low High VCC = MIN VCC = MAX VCC = MIN, IOL = 20A VCC = MIN, IOL = 24mA VCC = MIN, IOH = -3.2mA VCC = MIN, IOH = -20A VIN = GND VIN = VCC VOUT = VCC VOUT = GND VOUT = GND VCC = MAX, VIN = 0 or VCC8 VCC = MAX (CMOS inputs)5, 6 20 (Active)4 2.4 VCC - 0.1V -10 10 -0.3 2.0 0.8 VCC + 0.3 0.100 0.500 V V PARAMETER TEST CONDITION MIN TYP1 MAX UNIT
DC ELECTRICAL CHARACTERISTICS
Output voltage2 VOL VOH Low High V V V V A A A A mA A mA/MHz
Input current IIL IIH Low7 High
Output current IO(OFF) IOS ICC ICC/f Capacitance CI CB Input I/O VCC = 5V, VIN = 2.0V VB = 2.0V 12 15 pF pF Hi-Z state Short-circuit3 VCC supply current (Standby) VCC supply current 10 -10 -130 100 1.5
45
6 5 4
30 I CC(mA) 3 t PD 15 0 0 6 12 f(MHz) 18 24 30 2 1 0 100A -1 -2 0 20 40 60 80 100 120 140 160 180 200 OUTPUT CAPACITANCE LOADING (pF)
SP00018
SP00019
Figure 1. ICC vs (Worst Case)
Frequency5, 6
Figure 2. tPD vs Output Capacitance Loading (Typical)
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with TTL input levels: VIL = 0.45V, VIH = 2.4V. Measured with all outputs switching. 5. ICC/TTL input = 2mA. 6. ICC vs frequency (registered configuration) = 2mA/MHz. 7. IIL for Pin 1 (I0/CLK) is 10A with VIN = 0.4V. 8. VIN includes CLK and OE if applicable.
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
AC ELECTRICAL CHARACTERISTICS4 Commercial = 0C Tamb +75C, 4.75V VCC < 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V; R2 = 390
TEST CONDITION1 SYMBOL Pulse width tCKP tCKH tCKL tARW Hold time tIH Input or feedback data hold time CLK + Input 200 50 0 0 ns Clock period (Minimum tIS + tCKO) Clock width High Clock width Low Async reset pulse width CLK + CLK + CLK - I , F CLK + CLK - CLK + I +, F + 200 200 200 50 50 50 33 15 15 25 33 15 15 25 ns ns ns ns PARAMETER FROM TO R1 () CL (pF) PLC18V8Z25 (Commercial) MIN MAX PLC18V8ZIA (Industrial) MIN MAX UNIT
Setup time tIS Input or feedback data setup time I , F CLK + 200 50 18 18 ns
Propagation delay tPD tCKO tOE13 tOD12 tOD22 tOE23 tARD tARR tSPR tPPR Delay from input to active output Clock High to output valid access Time Product term enable to outputs off Product term disable to outputs off Pin 11 output disable High to outputs off Pin 11 output enable to active output Async reset delay Async reset recovery time Sync preset recovery time Power-up reset I , F CLK + I , F I , F OE - OE + I , F I , F I , F VCC + F F F F F F F+ CLK + CLK + F+ 20 20 25 200 200 Active-High R = 1.5k Active-Low R = 550 From VOH R = From VOL R = 200 From VOH R = From VOL R = 200 Active-High R = 1.5k Active-Low R = 550 50 50 50 5 5 50 25 15 25 25 20 20 30 20 20 25 25 15 25 25 20 20 30 ns ns ns ns ns ns ns ns ns ns
Frequency of operation fMAX Maximum frequency I/(tIS + tCKO) 200 50 30 30 MHz
NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. Resistor values of 1.5k and 550 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
AC ELECTRICAL CHARACTERISTICS4 Commercial = 0C Tamb +75C, 4.75V VCC < 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V; R2 = 390
TEST CONDITION1 SYMBOL Pulse width tCKP tCKH tCKL tARW Hold time tIH Input or feedback data hold time CLK + Input 200 50 0 0 ns Clock period (Minimum tIS + tCKO) Clock width High Clock width Low Async reset pulse width CLK + CLK + CLK - I , F CLK + CLK - CLK + I +, F + 200 200 200 50 50 50 47 20 20 35 57 25 25 40 ns ns ns ns PARAMETER FROM TO R1 () CL (pF) PLC18V8Z35 (Commercial) MIN MAX PLC18V8ZI (Industrial) MIN MAX UNIT
Setup time tIS Input or feedback data setup time I , F CLK + 200 50 25 30 ns
Propagation delay tPD tCKO tOE13 tOD12 tOD22 tOE23 tARD tARR tSPR tPPR Delay from input to active output Clock High to output valid access Time Product term enable to outputs off Product term disable to outputs off Pin 11 output disable High to outputs off Pin 11 output enable to active output Async reset delay Async reset recovery time Sync preset recovery time Power-up reset I , F CLK + I , F I , F OE - OE + I , F I , F I , F VCC + F F F F F F F+ CLK + CLK + F+ 25 25 35 200 200 Active-High R = 1.5k Active-Low R = 550 From VOH R = From VOL R = 200 From VOH R = From VOL R = 200 Active-High R = 1.5k Active-Low R = 550 50 50 50 5 5 50 35 22 35 35 25 25 35 30 30 40 40 27 40 40 40 30 40 ns ns ns ns ns ns ns ns ns ns
Frequency of operation fMAX Maximum frequency I/(tIS + tCKO) 200 50 21 18 MHz
NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. Resistor values of 1.5k and 550 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
POWER-UP RESET
In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC18V8Z. All internal registers will reset to Active-Low (logical "0") after a specified period of time (tPPR). Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (Q) of a registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition.
TIMING DIAGRAMS
VALID INPUT tIS tIH VALID INPUT tCKH tCKL
CLK
tCKP PIN 11 OE tCKO REGISTERED OUTPUTS tOD2 3-STATE tOE2
ANY INPUT PROGRAMMED FOR DIRECTION CONTROL
tPD
COMBINATORIAL OUTPUTS
Switching Waveforms
4.5V 3.0V
VCC
F (OUTPUTS)
I, B (INPUTS)
CLK
NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
1997 Aug 08
EEEE EEEE EEEEEEE EEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE
tPPR
1.5V tCKO
1.5V VOL +3V 1.5V 0V tCKL tIH 1.5V tIS tCKH tCKP 1.5V tCKL tIS +3V 1.5V 0V
1.5V
Power-Up Reset
SP00020
12
EEEEEEEE EEEEEEEE
tOD1 tOE1 3-STATE +5V 0V VOH
EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEE
EEE EEE
INPUTS I/O, REG. FEEDBACK
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
TIMING DIAGRAMS (Continued)
tARW ASYNCHRONOUS RESET INPUT tARD REGISTERED OUTPUT
tARR CLOCK
Asynchronous Reset
tIS SYNCHRONOUS PRESET INPUT tIH tSPR
CLOCK
tCKO REGISTERED OUTPUT
Synchronous Preset
SP00021
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and sequence.) To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, F0 - F7, must be enabled in order to read data out. The Q outputs of the registers will reflect data in as input via F0 - F7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via F0 - F7. Refer to the voltage waveform for timing and voltage references. tPL = 10sec.
REGISTER PRELOAD (DIAGNOSTIC MODE)
12.0V I9/OE (PIN 11) 5.0V tPL tPL 12.0V I5 (PIN 6) 5.0V tPL tPL tPL 5.0V tPL OE(VOL) 12.0V
I0/CLK (PIN 1) tOE tCKL PRELOAD DATA OUT tIS tIH tCKO DATA OUT
I0/CLK
F0-7
PRELOAD DATA IN
F0-7
I1-4, 6-8
1997 Aug 08
EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE
14
I1-4, 6-8
SP00022
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
LOGIC PROGRAMMING
The PLC18V8Z series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP design software package. ABELTM and CUPLTM design software packages also support the PLC18V8Z architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLC18V8Z logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the Program Table. Similarly, various OMC configurations are implemented by programming the Architecture Control bits AC1 and AC2. Note that the configuration cell is automatically programmed based on the OMC configuration. In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows:
OUTPUT POLARITY - (O, B)
S O, B X X S O, B
ACTIVE LEVEL INVERTING1
CODE L
ACTIVE LEVEL NON-INVERTING
CODE H
SP00023
"AND" ARRAY - (I, B)
I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B
P STATE DON'T CARE CODE - STATE INACTIVE1
P CODE O STATE I, B
P CODE H STATE I, B
P CODE L
SP00024
NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
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Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices PLC18V8Z
PROGRAM TABLE
NOTES: In the unprogrammed or virgin state: All AND gate locations are pulled to a logic "0" (Low). Output polarity is inverting. Pins 1 and 11 are configured as inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as combinatorial I/O, with the outputs disabled via the direction control term.
***
*
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
PURCHASE ORDER #
PROGRAM TABLE #
CUSTOMER NAME
PHILIPS DEVICE #
CONFIGURATION CELL (CLK/OE CONTROL) ARCH. CONTROL BITS OUTPUT POLARITY T AND OR (FIXED) E I F (I) F (B, O, D) R M 987654321076543210 7654321 0 D 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 D 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 D 19 A 20 A 21 A 22 A 23 A 24 A 25 A 26 A 27 D 28 A 29 A 30 A 31 A 32 A 33 A 34 A 35 A 36 D 37 A 38 A 39 A 40 A 41 A 42 A 43 A 44 A 45 D 46 A 47 A 48 A 49 A 50 A 51 A 52 A 53 A 54 D 55 A 56 A 57 A 58 A 59 A 60 A 61 A 62 A 63 64 65 66 67 68 69 70 71 SP AR 11 9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 PIN 0
CF(XXXX)
REV.
DATE
D A A A A A A A A 12 VARIABLE NAME AND ARRAY INACTIVE I, F (I, B) O H I, F (I, B) L **DON'T CARE - OMC ARCH. REGISTERED (D-TYPE) FIXED INPUT FIXED OUTPUT BIDIRECTIONAL I/O D I O B
CONTROL OUTPUT POLARITY NON-INVERTING INVERTING CONFIG. CELL* PIN 1 = CLK; PIN 11 = OE L PIN 1, PIN 11 = INPUT H H L
OR ARRAY (FIXED) DATA CANNOT BE ENTERED INTO THE OR ARRAY FIELD DUE TO THE FIXED NATURE OF THE DEVICE ARCHITECTURE. DIRECTION CONTROL D ACTIVE OUTPUT NOT USED A
* THE CONFIGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. ** FOR SP, AR: "-" IS NOT ALLOWED.
SP00029
1997 Aug 08
16
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
SNAP RESOURCE SUMMARY DESIGNATIONS
I0/CLK DINV8 NINV8 9 I1 AND PROGRAMMABLE AND ARRAY 36 ROWS X 72 COLUMNS 9 NOUTV8 OMC F6 CKEV8 NOUTV8 OMC F7 CLK I0 CONFIG. CELL
I2
9 NOUTV8 OMC F1
I7
9 I8 NOUTV8 OMC F0
SP AR OE CONFIG. CELL I9 I9/OE
1
FROM AND ARRAY
TO ALL OMCs
DIRECTION CONTROL TERM VCC
11 01 00 SP AR 10 OE MUX
XORREG
FROM AND ARRAY
OR S X(n) DFFV8 D OUTPUT POLARITY CONTROL Q CLK XORDIR NOUTV8 F
AC1n AC2n 00 10 11 01
XORINV
F MUX
FDMUX NOTE: Denotes a programmable cell location. TO ALL OMCs 11 OE OE11V8
SP00025
1997 Aug 08
17
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1997 Aug 08
18
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
PLCC20: plastic leaded chip carrier; 20 leads
SOT380-1
1997 Aug 08
19
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1997 Aug 08
20
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1997 Aug 08
21
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1997 Aug 08
22
Philips Semiconductors
Product specification
Zero standby power CMOS versatile PAL devices
PLC18V8Z
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 Aug 08 23

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